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CVE-2026-23213

Estado: AnalizadaMedia (5.5)—

In the Linux kernel, the following vulnerability has been resolved:

drm/amd/pm: Disable MMIO access during SMU Mode 1 reset

During Mode 1 reset, the ASIC undergoes a reset cycle and becomes temporarily inaccessible via PCIe. Any attempt to access MMIO registers during this window (e.g., from interrupt handlers or other driver threads) can result in uncompleted PCIe transactions, leading to NMI panics or system hangs.

To prevent this, set the `no_hw_access` flag to true immediately after triggering the reset. This signals other driver components to skip register accesses while the device is offline.

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A memory barrier `smp_mb()` is added to ensure the flag update is globally visible to all cores before the driver enters the sleep/wait state.

(cherry picked from commit 7edb503fe4b6d67f47d8bb0dfafb8e699bb0f8a4)

CVSS

Probabilidad de explotación (EPSS)

EPSS (Exploit Prediction Scoring System, de FIRST) estima la probabilidad de que una vulnerabilidad sea explotada en 30 días. Complementa a CVSS (impacto) y a CISA KEV (explotación confirmada).

Tecnologías afectadas (1)

Linux — Linux Kernel

CWE

Referencias

JSON original (NVD)

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{
  "id": "CVE-2026-23213",
  "cveTags": [],
  "metrics": {
    "cvssMetricV31": [
      {
        "type": "Primary",
        "source": "nvd@nist.gov",
        "cvssData": {
          "scope": "UNCHANGED",
          "version": "3.1",
          "baseScore": 5.5,
          "attackVector": "LOCAL",
          "baseSeverity": "MEDIUM",
          "vectorString": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H",
          "integrityImpact": "NONE",
          "userInteraction": "NONE",
          "attackComplexity": "LOW",
          "availabilityImpact": "HIGH",
          "privilegesRequired": "LOW",
          "confidentialityImpact": "NONE"
        },
        "impactScore": 3.6,
        "exploitabilityScore": 1.8
      }
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          "programFiles": [
            "drivers/gpu/drm/amd/amdgpu/amdgpu_device.c",
            "drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c",
            "drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c"
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          "programFiles": [
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            "drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c",
            "drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c"
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          "defaultStatus": "affected"
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  "published": "2026-02-18T15:18:42.600",
  "references": [
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      "tags": [
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      "url": "https://git.kernel.org/stable/c/c1853ebbec980d5c05d431bfd6ded73b1363fd00",
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      "tags": [
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      "source": "416baaa9-dc9f-4396-8d5f-8c081fb06d67"
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  ],
  "vulnStatus": "Analyzed",
  "weaknesses": [
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      "type": "Primary",
      "source": "nvd@nist.gov",
      "description": [
        {
          "lang": "en",
          "value": "NVD-CWE-noinfo"
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      ]
    }
  ],
  "descriptions": [
    {
      "lang": "en",
      "value": "In the Linux kernel, the following vulnerability has been resolved:\n\ndrm/amd/pm: Disable MMIO access during SMU Mode 1 reset\n\nDuring Mode 1 reset, the ASIC undergoes a reset cycle and becomes\ntemporarily inaccessible via PCIe. Any attempt to access MMIO registers\nduring this window (e.g., from interrupt handlers or other driver threads)\ncan result in uncompleted PCIe transactions, leading to NMI panics or\nsystem hangs.\n\nTo prevent this, set the `no_hw_access` flag to true immediately after\ntriggering the reset. This signals other driver components to skip\nregister accesses while the device is offline.\n\nA memory barrier `smp_mb()` is added to ensure the flag update is\nglobally visible to all cores before the driver enters the sleep/wait\nstate.\n\n(cherry picked from commit 7edb503fe4b6d67f47d8bb0dfafb8e699bb0f8a4)"
    },
    {
      "lang": "es",
      "value": "En el kernel de Linux, la siguiente vulnerabilidad ha sido resuelta:\n\ndrm/amd/pm: Deshabilitar el acceso MMIO durante el reinicio del Modo 1 de SMU\n\nDurante el reinicio del Modo 1, el ASIC se somete a un ciclo de reinicio y se vuelve temporalmente inaccesible a través de PCIe. Cualquier intento de acceder a los registros MMIO durante esta ventana (por ejemplo, desde manejadores de interrupciones u otros hilos del controlador) puede resultar en transacciones PCIe incompletas, lo que lleva a pánicos NMI o cuelgues del sistema.\n\nPara evitar esto, establecer la bandera 'no_hw_access' en verdadero inmediatamente después de activar el reinicio. Esto indica a otros componentes del controlador que omitan los accesos a registros mientras el dispositivo está fuera de línea.\n\nSe añade una barrera de memoria 'smp_mb()' para asegurar que la actualización de la bandera sea globalmente visible para todos los núcleos antes de que el controlador entre en el estado de suspensión/espera.\n\n(seleccionado de la confirmación 7edb503fe4b6d67f47d8bb0dfafb8e699bb0f8a4)"
    }
  ],
  "lastModified": "2026-06-17T10:21:06.793",
  "configurations": [
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}