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CVE-2025-63384

Estado: AnalizadaMedia (6.5)—

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

CVSS

Probabilidad de explotación (EPSS)

EPSS (Exploit Prediction Scoring System, de FIRST) estima la probabilidad de que una vulnerabilidad sea explotada en 30 días. Complementa a CVSS (impacto) y a CISA KEV (explotación confirmada).

Tecnologías afectadas (1)

Chipsalliance — Rocketchip

CWE

Referencias

JSON original (NVD)

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{
  "id": "CVE-2025-63384",
  "cveTags": [],
  "metrics": {
    "ssvcV203": [
      {
        "source": "134c704f-9b21-4f2e-91b3-4a467353bcc0",
        "ssvcData": {
          "id": "CVE-2025-63384",
          "role": "CISA Coordinator",
          "options": [
            {
              "exploitation": "none"
            },
            {
              "automatable": "no"
            },
            {
              "technicalImpact": "total"
            }
          ],
          "version": "2.0.3",
          "timestamp": "2025-11-12T20:38:19.765486Z"
        }
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    ],
    "cvssMetricV31": [
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        "cvssData": {
          "scope": "UNCHANGED",
          "version": "3.1",
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          "baseSeverity": "MEDIUM",
          "vectorString": "CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N",
          "integrityImpact": "NONE",
          "userInteraction": "NONE",
          "attackComplexity": "LOW",
          "availabilityImpact": "NONE",
          "privilegesRequired": "LOW",
          "confidentialityImpact": "HIGH"
        },
        "impactScore": 3.6,
        "exploitabilityScore": 2.8
      }
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  },
  "affected": [
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      "affectedData": [
        {
          "vendor": "n/a",
          "product": "n/a",
          "versions": [
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              "status": "affected",
              "version": "n/a"
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  "published": "2025-11-10T20:15:49.013",
  "references": [
    {
      "url": "https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET",
      "tags": [
        "Exploit",
        "Third Party Advisory"
      ],
      "source": "cve@mitre.org"
    },
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      "url": "https://github.com/chipsalliance/rocket-chip.git",
      "tags": [
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      ],
      "source": "cve@mitre.org"
    }
  ],
  "vulnStatus": "Analyzed",
  "weaknesses": [
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      "source": "134c704f-9b21-4f2e-91b3-4a467353bcc0",
      "description": [
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          "value": "CWE-266"
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  "descriptions": [
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      "lang": "en",
      "value": "A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability."
    },
    {
      "lang": "es",
      "value": "Se descubrió una vulnerabilidad en RISC-V Rocket-Chip v1.6 y versiones anteriores, donde la instrucción SRET (Supervisor-mode Exception Return) no logra transicionar correctamente el nivel de privilegio del procesador. En lugar de bajar de categoría desde el modo Máquina (M-mode) a modo Supervisor (S-mode) según lo especificado por el bit sstatus.SPP, el procesador permanece incorrectamente en M-mode, lo que lleva a una vulnerabilidad crítica de retención de privilegios."
    }
  ],
  "lastModified": "2026-06-17T09:53:03.867",
  "configurations": [
    {
      "nodes": [
        {
          "negate": false,
          "cpeMatch": [
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  "sourceIdentifier": "cve@mitre.org"
}