CVE-2025-22045
Estado: ModificadaMedia (5.5)—
In the Linux kernel, the following vulnerability has been resolved:
x86/mm: Fix flush_tlb_range() when used for zapping normal PMDs
On the following path, flush_tlb_range() can be used for zapping normal PMD entries (PMD entries that point to page tables) together with the PTE entries in the pointed-to page table:
The arm64 version of flush_tlb_range() has a comment describing that it can be used for page table removal, and does not use any last-level invalidation optimizations. Fix the X86 version by making it behave the same way.
Currently, X86 only uses this information for the following two purposes, which I think means the issue doesn't have much impact:
Leer descripción completaMostrar menos
- In native_flush_tlb_multi() for checking if lazy TLB CPUs need to be IPI'd to avoid issues with speculative page table walks. - In Hyper-V TLB paravirtualization, again for lazy TLB stuff.
The patch "x86/mm: only invalidate final translations with INVLPGB" which is currently under review (see <https://lore.kernel.org/all/20241230175550.4046587-13-riel@surriel.com/>) would probably be making the impact of this a lot worse.
Detalles técnicos trazas, registros y código del informe original
collapse_pte_mapped_thp
pmdp_collapse_flush
flush_tlb_rangeCVSS
- Versión: 3.1
- Vector: CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H
- Puntuación base: 5.5
Probabilidad de explotación (EPSS)
- Probabilidad de explotación en los próximos 30 días: 0.24%
- Percentil entre todas las CVEs puntuadas: 14
- Fecha de la puntuación: 5/10/2026
EPSS (Exploit Prediction Scoring System, de FIRST) estima la probabilidad de que una vulnerabilidad sea explotada en 30 días. Complementa a CVSS (impacto) y a CISA KEV (explotación confirmada).
Tecnologías afectadas (1)
CWE
- NVD-CWE-noinfo
Referencias
- https://git.kernel.org/stable/c/0708fd6bd8161871bfbadced2ca4319b84ab44fe
- https://git.kernel.org/stable/c/0a8f806ea6b5dd64b3d1f05ff774817d5f7ddbd1
- https://git.kernel.org/stable/c/320ac1af4c0bdb92c864dc9250d1329234820edf
- https://git.kernel.org/stable/c/3ef938c3503563bfc2ac15083557f880d29c2e64
- https://git.kernel.org/stable/c/556d446068f90981e5d71ca686bdaccdd545d491
- https://git.kernel.org/stable/c/618d5612ecb7bfc1c85342daafeb2b47e29e77a3
- https://git.kernel.org/stable/c/7085895c59e4057ffae17f58990ccb630087d0d2
- https://git.kernel.org/stable/c/78d6f9a9eb2a5da6fcbd76d6191d24b0dcc321be
- https://git.kernel.org/stable/c/93224deb50a8d20df3884f3672ce9f982129aa50
- https://lists.debian.org/debian-lts-announce/2025/05/msg00030.html
- https://lists.debian.org/debian-lts-announce/2025/05/msg00045.html
JSON original (NVD)
Mostrar
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"value": "In the Linux kernel, the following vulnerability has been resolved:\n\nx86/mm: Fix flush_tlb_range() when used for zapping normal PMDs\n\nOn the following path, flush_tlb_range() can be used for zapping normal\nPMD entries (PMD entries that point to page tables) together with the PTE\nentries in the pointed-to page table:\n\n collapse_pte_mapped_thp\n pmdp_collapse_flush\n flush_tlb_range\n\nThe arm64 version of flush_tlb_range() has a comment describing that it can\nbe used for page table removal, and does not use any last-level\ninvalidation optimizations. Fix the X86 version by making it behave the\nsame way.\n\nCurrently, X86 only uses this information for the following two purposes,\nwhich I think means the issue doesn't have much impact:\n\n - In native_flush_tlb_multi() for checking if lazy TLB CPUs need to be\n IPI'd to avoid issues with speculative page table walks.\n - In Hyper-V TLB paravirtualization, again for lazy TLB stuff.\n\nThe patch \"x86/mm: only invalidate final translations with INVLPGB\" which\nis currently under review (see\n<https://lore.kernel.org/all/20241230175550.4046587-13-riel@surriel.com/>)\nwould probably be making the impact of this a lot worse."
},
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"value": "En el kernel de Linux, se ha resuelto la siguiente vulnerabilidad: x86/mm: Arregla flush_tlb_range() cuando se usa para zapping de PMD normales En la siguiente ruta, flush_tlb_range() se puede usar para zapping de entradas PMD normales (entradas PMD que apuntan a tablas de páginas) junto con las entradas PTE en la tabla de páginas apuntada: colapso_pte_mapped_thp pmdp_collapse_flush flush_tlb_range La versión arm64 de flush_tlb_range() tiene un comentario que describe que se puede usar para la eliminación de la tabla de páginas y no usa ninguna optimización de invalidación de último nivel. Arregla la versión X86 haciendo que se comporte de la misma manera. Actualmente, X86 solo usa esta información para los dos propósitos siguientes, lo que creo que significa que el problema no tiene mucho impacto: - En native_flush_tlb_multi() para verificar si las CPU TLB perezosas necesitan ser IPI'd para evitar problemas con recorridos especulativos de la tabla de páginas. En la paravirtualización de TLB de Hyper-V, de nuevo para problemas de TLB lentos. El parche \"x86/mm: solo invalidar las traducciones finales con INVLPGB\", actualmente en revisión (véase ), probablemente estaría agravando considerablemente el impacto de esto."
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