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CVE-2020-25602

Estado: ModificadaMedia (6)—

An issue was discovered in Xen through 4.14.x. An x86 PV guest can trigger a host OS crash when handling guest access to MSR_MISC_ENABLE. When a guest accesses certain Model Specific Registers, Xen first reads the value from hardware to use as the basis for auditing the guest access. For the MISC_ENABLE MSR, which is an Intel specific MSR, this MSR read is performed without error handling for a #GP fault, which is the consequence of trying to read this MSR on non-Intel hardware. A buggy or malicious PV guest administrator can crash Xen, resulting in a host Denial of Service.

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Only x86 systems are vulnerable. ARM systems are not vulnerable. Only Xen versions 4.11 and onwards are vulnerable. 4.10 and earlier are not vulnerable. Only x86 systems that do not implement the MISC_ENABLE MSR (0x1a0) are vulnerable. AMD and Hygon systems do not implement this MSR and are vulnerable. Intel systems do implement this MSR and are not vulnerable. Other manufacturers have not been checked. Only x86 PV guests can exploit the vulnerability. x86 HVM/PVH guests cannot exploit the vulnerability.

CVSS

Probabilidad de explotación (EPSS)

EPSS (Exploit Prediction Scoring System, de FIRST) estima la probabilidad de que una vulnerabilidad sea explotada en 30 días. Complementa a CVSS (impacto) y a CISA KEV (explotación confirmada).

Tecnologías afectadas (4)

CWE

Referencias

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      "value": "An issue was discovered in Xen through 4.14.x. An x86 PV guest can trigger a host OS crash when handling guest access to MSR_MISC_ENABLE. When a guest accesses certain Model Specific Registers, Xen first reads the value from hardware to use as the basis for auditing the guest access. For the MISC_ENABLE MSR, which is an Intel specific MSR, this MSR read is performed without error handling for a #GP fault, which is the consequence of trying to read this MSR on non-Intel hardware. A buggy or malicious PV guest administrator can crash Xen, resulting in a host Denial of Service. Only x86 systems are vulnerable. ARM systems are not vulnerable. Only Xen versions 4.11 and onwards are vulnerable. 4.10 and earlier are not vulnerable. Only x86 systems that do not implement the MISC_ENABLE MSR (0x1a0) are vulnerable. AMD and Hygon systems do not implement this MSR and are vulnerable. Intel systems do implement this MSR and are not vulnerable. Other manufacturers have not been checked. Only x86 PV guests can exploit the vulnerability. x86 HVM/PVH guests cannot exploit the vulnerability."
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      "value": "Se detectó un problema en Xen versiones hasta 4.14.x. Un invitado PV x86 puede desencadenar un bloqueo del Sistema Operativo del host cuando maneja el acceso de invitado para MSR_MISC_ENABLE. Cuando un invitado accede a ciertos registros específicos del modelo, Xen primero lee el valor del hardware para usarlo como base para auditar el acceso de invitado. Para el MSR MISC_ENABLE, que es un MSR específico de Intel, esta lectura de MSR se realiza sin manejo de errores para un fallo #GP, que es la consecuencia de intentar leer este MSR en hardware que no es de Intel. Un administrador invitado de PV con errores o malicioso puede bloquear Xen y  causar una Denegación de Servicio del host. Solo los sistemas x86 son vulnerables. Los sistemas ARM no son vulnerables. Solo las versiones de Xen 4.11 y posteriores son vulnerables. Las versiones 4.10 y anteriores no son vulnerables. Solo los sistemas x86 que no implementan MISC_ENABLE MSR (0x1a0) son vulnerables. Los sistemas AMD e Hygon no implementan este MSR y son vulnerables. Los sistemas Intel implementan este MSR y no son vulnerables. No se han comprobado otros fabricantes. Solo los invitados PV x86 pueden explotar la vulnerabilidad. Los invitados HVM/PVH x86 no pueden explotar la vulnerabilidad."
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  "lastModified": "2026-06-17T03:06:57.740",
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